Introduction to exception interrupts and vector tables

 Introduction to exception interrupts and vector tables

Exceptions arise whenever the normal flow of a program has to be halted temporarily,

for example, to service an interrupt from a peripheral. Before attempting to handle an

exception, the ARM7TDMI processor preserves the current processor state so that the

original program can resume when the handler routine has finished.

When an exception occurs, for example an IRQ exception, the following actions are taken:

First the address of the next instruction to be executed (PC + 4) is saved into the link

Register(LR). Then the CPSR is copied into the SPSR of the exception mode that is about to be

entered (i.e. SPSR_irq). The PC is then filled with the address of the exception mode

interrupt vector. In the case of the IRQ mode this is 0x00000018(See Vector Table 2.6). At the same time the mode is changed to IRQ mode, which causes R13 and R14 to be replaced by the IRQ R13 and R14 registers. On entry to the IRQ mode, the I bit in the CPSR is set, causing the IRQ interrupt line to be disabled. If you need to have nested IRQ interrupts, your code must manually re-enable the IRQ interrupt and push the link register onto the stack in order to preserve the original return address. From the exception interrupt vector your code will jump to the exception ISR. The first thing your code must do is to preserve any of the registers R0-R12 that the ISR will use by pushing them onto the IRQ stack. Once this is done you can begin processing the exception. When an exception occurs the CPU will change modes and jump to the associated interrupt vector. Once your code has finished processing the exception it must return back to the user mode and continue where it left off. However the ARM instruction set does not contain a “return” or “return from interrupt” instruction so manipulating the PC must be done by regular instructions. The situation is further complicated by there being a number of different return cases. First of all, consider the SWI instruction. In this case the SWI instruction is executed, the address of the next instruction to be executed is stored in the Link register and the exception is processed. In order to return from the exception all that is necessary is to move the contents of the link register into the PC and processing can continue. However in order to make the CPU switch modes back to user mode, a modified version of the move