LPC 2148(ARM7) Development Board

LPC 2148(ARM7) Development Board

The principle feature of the ARM 7 microcontroller is that it is a register based load-and-store architecture with a number of operating modes. While the ARM7 is a 32 bit microcontroller, it is also capable of running a 16-bit instruction set, known as “THUMB”. This helps it achieve a greater code density and enhanced power saving. While all of the register-to-register data processing instructions are single-cycle, other instructions such as data transfer instructions, are multi-cycle. To increase the performance of these instructions, the ARM 7 has a three-stage pipeline. Due to the inherent simplicity of the design and low gate count, ARM 7 is the industry leader in low-power processing on a watts per MIP basis. Finally, to assist the developer, the ARM core has a built-in JTAG debug port and on-chip “embedded ICE” that allows programs to be downloaded and fully debugged in-system.ARM processors are typical of RISC (Reduced Instruction Set Computers) processors in that they implement a load and store architecture. Only load and store instructions can access memory. Data processing instructions operate on register contents only. The RISC philosophy is implemented with four major design rules: 

The following list gives some the silent features of ARM7 processor

•         32-bit RISC-processor core (32-bit instructions)
•         37 pieces of 32-bit integer registers (16 available)
•         Pipelined (ARM7: 3 stages)
•         Cached (depending on the implementation)
•         Von Neuman-type bus structure (ARM7), Harvard (ARM9)
•         8 / 16 / 32 -bit data types
•         7 modes of operation (usr, fiq, irq, svc, abt, sys, und)
•         Simple structure ,reasonably good speed / power consumption ratio
•         Fully 32-bit instruction set in native operating mode
•         32-bit long instruction word
•         All instructions are conditional
•         Normal execution with condition AL (always)
•         For a RISC-processor, the instruction set is quite diverse with different  addressing modes
•         36 instruction formats
•         All instructions are conditional
•         In normal instruction execution (unconditional) condition field contents of AL is used (Always)
•         In conditional operations one of the 14 available conditions is selected