Structure of Current Program Status Register (CPSR)

Structure of Current Program Status Register (CPSR)

In addition to the register bank there is an additional 32 bit wide register called the ‘currentprogram status register’ (CPSR). The CPSR contains a number of flags which report andcontrol the operation of the ARM7 CPU.

Fig2. 4 Current Program Status Register and Flags reference

The top four bits (28 to 31) of the CPSR contain the condition codes which are set by the CPU. The condition codes report the result status of a data processing operation. From the condition

codes you can tell if a data processing instruction generated a negative (N), zero(Z), carry(C) or

overflow (V) result. The lower eight bits (0 to 7) in the CPSR contain flags which may be set or cleared by the application code. Bits 7 and 8 are the I and F bits. These bits are used to enable and disable the two interrupt sources which are external to the ARM7 CPU. You should be careful when programming these two bits because in order to disable either interrupt source the bit must be set to ‘1’ not ‘0’ as you might expect. Bit 5 is the THUMB bit.

Condition Code flags:  There are four bits Bit 28 to bit 31 are kept aside for representing the status of a data processing operation. Functions of these flags are as follows.

Negative Flag Bit(31):  This flag bit indicates the result of an arithmetic or logical operation is negative. It is set 1 if result of arithmetic or logical operation is negative otherwise it is reset to 0.

Zero Flag (Bit 30): Set and reset according to the flag setting operation is zero or not. It records zero condition. It is set 1 if result of arithmetic or logical operation is zero otherwise it is reset to 0.

Carry Flag (Bit 29): This can also be called as Unsigned overflow Flag. Set and reset according to the flag setting operation results in a carry or not. It is set 1 if result of 32 bit arithmetic operation generates carry, otherwise it is reset to 0.